This invention relates to image sensor array configurations for reducing image array pixel reset noise. More specifically, the invention relates to pixel designs for resetting pixels in a manner that reduces pixel reset noise.
CMOS image sensors are attractive due to the compatibility with VLSI circuits. However, CMOS imagers have typically higher noise than CCD imagers. While CCD imagers employ correlated double-sampling (CDS) to remove the reset noise commonly referred to as kTC noise, the operation of most CMOS imagers does not allow for true CDS. Instead, uncorrelated double-sampling is typically employed to remove the constant reset level. Unfortunately, this method often actually increases reset noise.
There have been proposed various CMOS pixel designs that incorporate correlated-doubling sampling functionality in the pixel itself. Although such circuits are found to often substantially remove the reset noise, in general such designs require the inclusion of an amplifier device and two additional devices that are necessary within each pixel to provide the CDS functionality. This added circuitry greatly increases the area of the pixel. In particular, the inclusion of a separate amplifier in each pixel substantially increases the size and cost of an imaging array of such pixels. As a result, a tradeoff between CDS functionality and imager array size and cost has typically been required.